1. Field of the Invention
The present invention relates to a method of manufacturing a non-volatile semiconductor memory device and, particularly, to a method of manufacturing a semiconductor memory device comprising, on a substrate, a non-volatile memory transistor having a double layer gate electrode structure and a transistor having a single layer gate electrode structure for a peripheral circuit.
2. Description of the Prior Art
A non-volatile semiconductor memory device, as exemplified by an EPROM which has a double layer gate electrode structure, is under development, and, recently, its cell integration density and cell size have been rapidly increasing and reducing, respectively.
There are various recent proposals concerning increase of integration density of the EPROM, one of which is a self align contact (SAC) in which a contact to a source region of a memory transistor is formed in a side wall provided on a side face of the memory transistor in a self align method. Another proposal is to provide, for reducing the gate size of a transistor for a peripheral circuit, an LDD (Lightly Doped Drain) structure having a low impurity density diffusion layer region in the adjacent of an edge portion of a transistor gate.
It is known, in an EPROM, to form on a single substrate a memory cell, comprising a double layer gate transistor having a floating gate, and a single layer gate transistor for a peripheral circuit.
A method of manufacturing a conventional non-volatile semiconductor will be described with reference to FIG. 1a to 1l.
First, as shown in FIG. 1a, a peripheral circuit active region 21 and a memory cell active region 22 are separated by providing a field oxide 2 on a surface of a semiconductor substrate 1 of silicon, and then a first gate insulating layer 3 is formed on the active regions 21 and 22. Thereafter, a polysilicon (poly-crystalline silicon) layer is deposited thereon, and a first electrode layer 4 is formed on the active region 22 by patterning the polysilicon layer.
Then, as shown in FIG. 1b, the first gate insulating layer 3 on only the active region 21 is removed, and a second gate insulating layer 9 of silicon oxide is formed on the semiconductor substrate 1 and the first electrode layer 4 to form a second electrode layer 10 of polysilicon. Then, a first insulating layer 6 of silicon oxide is formed on the whole surface. The first insulating layer 6 functions to insulate a control electrode gate of the memory cell transistor from an SAC during formation of the transistor.
Then, as shown in FIG. 1c, a patterned photoresist layer 27 is formed on the first insulating layer 6. The first insulating layer 6 and the second electrode layer 10 are sequentially etched by using the patterned photoresist layer 27 as a mask to form an electrode gate of the active region 22.
Thereafter, as shown in FIG. 1d, the photoresist layer 27 is removed, and a photoresist layer 28 covering the active region 21 is formed selectively. The second gate insulating layer 9 and the first electrode layer 4 are sequentially etched away by using the first insulating layer 6 as a mask. With this step, there is formed a second electrode gate having the control gate and a floating gate.
Then, as shown in FIG. 1e, a cell source/drain region 14 is formed by using the photoresist layer 28 and the second electrode gate on the active region 22 as a mask. Thereafter, the photoresist layer 28 is removed, and a photoresist layer 29 covering the active region 22 is formed. A low impurity density source/drain region 5 is formed by using the photoresist layer 29 and the electrode gate on the active region 21.
Thereafter, as shown in FIG. 1f, the photoresist layer 29 is removed, and then a second insulating layer 13 of silicon oxide is formed on the whole surface. The photoresist layer 29 is necessary to form side walls on side faces of the gate when the LDD structure of the transistor for the peripheral circuit is provided.
Then, as shown in FIG. 1g, the side walls are formed on the side faces of the gate on the active regions 21 and 22 by etching back the second insulating layer 13, and then a photoresist layer 30 is formed. The photoresist layer 30 is patterned so that it covers the active region 22, and a source/drain region 7 in the active region 21 is formed with the gate including the side-wall as a mask, resulting in the transistor having an LDD structure for the peripheral circuit.
Then, as shown in FIG. 1h, the photoresist layer 30 is removed, and a third insulating layer 15 of silicon oxide is formed on the whole surface. The third insulating layer 15 is necessary to form side walls on side faces of the gate of the memory cell transistor and also is necessary to form the SAC of the memory cell transistor.
Then, as shown in FIG. 1i, the third insulating layer 15 is etched back with a photoresist layer (not shown), selectively provided as a mask such that only the source side of the transistor in the active region 22 is exposed, and, further, the first gate insulating layer 3 is also etched to form a first contact hole 16 in the third insulating layer 15 on the side face of the gate of the memory cell transistor on the source side thereof.
Then, as shown in FIG. 1j, a tungsten silicide layer is deposited on the whole surface, and a source electrode 17 is formed by patterning the silicide layer.
Then, as shown in FIG. 1k, a first interlayer insulating layer 8 of TEOS BPSG is formed on the whole surface.
Thereafter, as shown in FIG. 1l, a second contact hole 19 is formed on the interlayer insulating layer 8, and then a metal electrode 20 of aluminum, etc., is selectively formed.
The above described method of manufacturing a non-volatile semiconductor memory device has the following problems:
(A) Since the gate insulating layer on the floating gate of the memory cell transistor and the gate insulating layer of the transistor for the peripheral circuit are formed simultaneously, it is impossible to obtain optimum layer quality and layer thickness for the respective transistor.
The same method of manufacturing a non-volatile semiconductor memory device is disclosed in U.S. Pat. No. 4,775,642 issued Oct. 4, 1988. This patent discloses that the gate insulating layer, on the floating gate, and the gate insulating layer of the transistor for the peripheral circuit are formed simultaneously.
(B) For the same reason, it is necessary to form the insulating layer 6, for insulating the control gate from the SAC of the memory cell transistor, in forming the SAC, before formation of the control gate electrode. As a result, the insulating layer 6, also formed on the gate of the transistor for the peripheral circuit region, is degraded.
(C) The sidewall which is necessary to provide the transistor for the peripheral circuit with the LDD structure is also formed on the side faces of the gate of the memory cell transistor. Therefore, when sidewalls are formed for protection of the side faces of the gate, which sidewalls are necessary in forming the SAC of the memory cell transistors, the thickness of the sidewall of the memory cell transistor is doubled. As a result, the distance between adjacent sidewalls in the source region becomes small, thereby causing the contact area of the SAC to be small, and leading to an increase of contact resistance.